Operating System DesignSIMMAC is a machine that contains a word-addressable memory of size 512, and an ALU for its arithmetic operations. Each instruction of SIMMAC consists of a 32-bit word in which the leftmost 16 bits are reserved for the opcode and the rightmost 16 bits are reserved for the operand. SIMMAC
- Accumulator(ACC) which is involved in all arithmetic operations
- Storage Address Register(SAR) which is involved in all references to primary storage. SAR holds the address of the data
- Storage Data Register(SDR) which is also involved in all references to primary storage. SDR holds the data specified in SAR
- Primary Storage Instruction Address Register(PSIAR) which points to the location of the next machine instruction in primary storage
- Temporary Register(TMPR) which is used (in this implementation) to hold the value of ACC while ACC is being used to increment PSIAR
- Control Storage Instruction Address Register(CSIAR) which points to the location of the next micro-instruction to be executed. I did not use this register
- Instruction Register(IR) which holds the current instruction being executed(not used).
- Micro-instruction Register(MIR) which holds the current micro-instruction being executed (not used).
- ADD (Opcode = 10) ADD
- SUB (Opcode = 20) SUB
- LDA ( Opcode = 30) LDA
- STR (Opcode = 40) STR
- BRH ( Opcode = 50) BRH
- CBR (Opcode = 60) CBR
- LDI ( Opcode = 70) LDI
- HALT ( Opcode = 5) HALT<0>
MemorySIMMAC has a main memory array of size 512 to hold words of 32 bits in size. The main memory was designed to hold instructions from index 0 to 200 and data from index 201 to 511. Data are loaded by assigning the integer values to the corresponding positions in the main memory. The location of data was selected to include positions 201, 202, 301, and 302 to satisfy the requirements for programs 4 and 5 (processes 3 and 4 in SIMMAC). Because some instructions request more CPU time than the time quantum in a multitasking system using a round-robin, it is important that the status of the registers be saved until the scheduler comes back to finish the same process. The status of the process is usually stored in a process control block data structure. In SIMMAC, the status of each register is saved in array y, while array y is stored for each active process in a two-dimensional array PCB.
| Process Control Block |
|ACC | SAR | SDR | PSIAR | TMPR | HALT |