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Operating System Design 

SIMMAC is a machine that contains a word-addressable memory of size 512, and an ALU for its arithmetic operations. Each instruction of SIMMAC consists of a 32-bit word in which the leftmost 16 bits are reserved for the opcode and the rightmost 16 bits are reserved for the operand. SIMMAC

Registers:

  • Accumulator(ACC) which is involved in all arithmetic operations
  • Storage Address Register(SAR) which is involved in all references to primary storage. SAR holds the address of the data
  • Storage Data Register(SDR) which is also involved in all references to primary storage. SDR holds the data specified in SAR
  • Primary Storage Instruction Address Register(PSIAR) which points to the location of the next machine instruction in primary storage
  • Temporary Register(TMPR) which is used (in this implementation) to hold the value of ACC while ACC is being used to increment PSIAR
  • Control Storage Instruction Address Register(CSIAR) which points to the location of the next micro-instruction to be executed. I did not use this register
  • Instruction Register(IR) which holds the current instruction being executed(not used).
  • Micro-instruction Register(MIR) which holds the current micro-instruction being executed (not used).

Instructions

Instruction:                                                 Format:
  • ADD (Opcode = 10) ADD <address>
  • SUB (Opcode = 20) SUB <address>
  • LDA ( Opcode = 30) LDA <address>
  • STR (Opcode = 40) STR <address>
  • BRH ( Opcode = 50) BRH <address>
  • CBR (Opcode = 60) CBR <address>
  • LDI ( Opcode = 70) LDI<value>
  • HALT ( Opcode = 5) HALT<0>
SIMMAC is designed to read text files containing processes or programs written in its language. Each line of the text file contains a process or program starting with the process number, the arrival time, and CPU time the process needs. The CPU time is the number of instructions in each process, where each instruction is a clock cycle and the time quantum, specified by the user, is an integer multiple of a clock cycle. In this way, the round-robin scheduler can execute each program for the time quantum and cycle through all the programs, thus allocating an equivalent CPU time to each program while making efficient use of the CPU at all times. The language of SIMMAC specifies that each instruction is written as shown in figure 1. In my implementation, SIMMAC’s language is written in 32-bit hexadecimal instructions, which are then split into opcode and operand before being executed. Because I separated the opcode from operand before execution, I did not use the micro-instructions where the TMPR register extracts the address portion of the instruction and places it in register SAR, then placing the integer corresponding to the location of SAR in main memory into register SDR. Although my design is a variation of the required design, it was advantageous because, for every instruction that contains such a sequence of micro-instructions, I saved the time required to process those three micro-instructions. To keep track of the locations of the start and end of each process, a tracker array was specified that stores the index of start and end for each process in the main memory. This facilitates access to each process whenever they are executed.

Memory

SIMMAC has a main memory array of size 512 to hold words of 32 bits in size. The main memory was designed to hold instructions from index 0 to 200 and data from index 201 to 511. Data are loaded by assigning the integer values to the corresponding positions in the main memory. The location of data was selected to include positions 201, 202, 301, and 302 to satisfy the requirements for programs 4 and 5 (processes 3 and 4 in SIMMAC). Because some instructions request more CPU time than the time quantum in a multitasking system using a round-robin, it is important that the status of the registers be saved until the scheduler comes back to finish the same process. The status of the process is usually stored in a process control block data structure. In SIMMAC, the status of each register is saved in array y, while array y is stored for each active process in a two-dimensional array PCB.

__________________________

| Process Control Block                               |

|ACC | SAR | SDR | PSIAR | TMPR | HALT |  

Schedule

SIMMAC uses a round-robin algorithm for process scheduling. Processes are read from a text file, placed in main memory, instruction by instruction, and then retrieved and added to the job queue. Round robin then allocates an equal amount of CPU time for each process until a time quantum has passed and the number of instructions executed is equal to a quantum. At this point, array y stores the current state of the registers for the next round( if quantum is less than the length of the process) and round-robin switches context to the next job. The algorithm keeps looping through the processes/jobs until all of them have been fully executed.

Programs

A total of five SIMMAC programs or processes were written in SIMMAC’s language. The execution of the five programs shows the functionality of the different instructions such as ADD, SUB, and CBR. The first three programs add twenty integers in different locations in the main memory and store the sum in a different location in memory. The fourth process takes an integer (=> 100) in location 201 in main memory and decrements it by 1 until it is zero and the result is stored in location 202. This process tests SIMMAC’s subtract, conditional branch, and store instructions. The fifth process takes the integer in location 301 and increments its value by two until its value has increased by 200, and stores the result in location 302 in main memory. This is the most complex process because a counter (=100) is necessary to know when the integer has been increased by 200. By having a counter (=100) and decrementing it by 1 each time, while incrementing the value by 2, the conditional branch instruction “knows” if the value has been increased by 200 or not. If the counter is not zero, the value has not been increased by 200. This process tests addition, subtraction, conditional branch, and store in the same process.